MIPS Processor Design

Old, pending renewal.

In CPRE 381, our team implemented single cycle and pipelined processors based on the MIPS ISA (Instruction Set Architecture). The single cycle processor was an introductory implementation focused on educating us on the ways in which to take the core instruction set found on the MIPS Green Sheet and implementing it into hardware. This part of the project required creation of main function units within the processor like the Program Counter, Register File, ALU (Arithmetic Logic Unit), and the necessary logic to integrate all of these components to achieve desired functionality. The pipelined processor took this single cycle base and added “pipelines” or stages to the processor. This is a more accurate representation, albeit on a much smaller scale, of how processors today are designed. Additionally, software and hardware hazard detection was introduced as pipelines can cause data synchronization issues. My primary role in this project was in ALU design/testing and integrating all of the components together for the main processor.

Additionally, our team got hands-on experience working with VHDL (a hardware description language) to program the processor. More specifically, we got insight into dataflow and structural concurrent programming methods. There was also a toolflow designed by the TAs which helped us to debug the processor, helping us to gain invaluable experience in problem solving at the hardware level. At the end of design, testing, and validation of each part of the project, we ran synthesis on the design to convert from RTL to GL (Gate Level) to understand critical paths (the paths which instructions travel through the processor) and the frequency our processor runs at. This allowed us to, at the end of the semester, analyze both processors to see which performed better.

This project served as one of the main learning experiences in team-based projects that had an influential affect on my work ability. Working with my team, we were able to start completely from scratch (unlike other projects which gave a basis to start from) and implement a working processor at the end. This gave numerous benefits to both myself and my teammates that showed us how to approach a problem from an engineering perspective and employ problem solving techniques to reach the end goal. Additionally, it taught us a lot in terms of time-management and resource allocation methodologies. Being faced with a large project like this, it was extremely important that each of us carved out time as possible throughout our busy schedules to work on the functional components within the processor.